A memory tester performs a test on memory devices by supplying a sequence of addresses and data patterns to the device under test (DUT), by reading the output from the DUT consisting of a series of test signals which create a test signal pattern and thereby determining if the DUT passed or failed the test. The output pin of the DUT is coupled to the receiver circuitry of the device tester which compares the test signal pattern on the output pin of the DUT with a reference test signal pattern stored within the tester to determine whether the DUT passed or failed the test.
Memory devices are available with various configurations and various numbers of outputs. For example, the one megabit dynamic random access memory (1M DRAM) device TMS4C1024 manufactured by Texas Instruments has a one megabit by one data I/O pin configuration, while the 1M DRAM TMS44C256 also manufactured by Texas Instruments has a 256 kilobit by four data I/O pins (256K.times.4) configuration. Even though the configuration and number of data I/O pins of these two devices is dissimilar, both of these devices are 1 MB DRAM devices.
For example, a memory tester may have four transceiver circuits and requires the connection of a separate transceiver circuit to each memory device data input/output pin to perform a device test. Therefore, one tester transceiver circuit is required to test a memory device having the 1M.times.1 configuration. A total of four memory devices in the 1M.times.1 configuration can be tested at once on this device tester which contains four transceiver circuits. Comparatively, testing a 1 MB DRAM in the 256K.times.4 configuration requires the use of four tester transceiver circuits per memory device, which therefore occupies the entire tester. In summary, because this device tester has only four receiver circuits, four 1M.times.1 configuration devices or only one 256K.times.4 configuration device can be tested at once. As a result, the number of devices a tester can test in parallel decreases with increasing number of data input/output pins on each device.
Using current tester design methodologies, many testers are incapable of economically testing wide I/O devices. The cost of redesigning a tester to add more receivers is cost prohibitive as receivers are complex and therefore very expensive. Tester manufacturers invest one to two years of design effort to double a particular tester's throughput capability through redesigning the memory algorithm generator.
There is a problem in finding a way to economically test wide data I/O memory devices.